The relave grid is a standard rectangular grid in which each grid element is the same size. For
example, the following Verilog code example results in an eight-slice-high column with an FD cell
in each slice:
(* RLOC = "X0Y0" *) FD sr0 (.C(clk), .D(d[0]), .Q(y[0]));
(* RLOC = "X0Y1" *) FD sr1 (.C(clk), .D(d[1]), .Q(y[1]));
(* RLOC = "X0Y2" *) FD sr2 (.C(clk), .D(d[2]), .Q(y[2]));
(* RLOC = "X0Y3" *) FD sr3 (.C(clk), .D(d[3]), .Q(y[3]));
(* RLOC = "X0Y4" *) FD sr4 (.C(clk), .D(d[4]), .Q(y[4]));
(* RLOC = "X0Y5" *) FD sr5 (.C(clk), .D(d[5]), .Q(y[5]));
(* RLOC = "X0Y6" *) FD sr6 (.C(clk), .D(d[6]), .Q(y[6]));
(* RLOC = "X0Y7" *) FD sr7 (.C(clk), .D(d[7]), .Q(y[7]));
BEL/LOC Constraints
For complex structures, the BEL or LOC constraints may need to be specied in addion to the
RLOC. The BEL constraint must be used to align the cells inside the RPM set, for example, to
align the LUTs with the registers. The LOC constraint is uncommon and typically not used
because the RPM set is forced on a specic site in the device and cannot be moved by the placer.
Whenever some BEL or LOC constraints need to be specied, it is important to not mix the
source of those constraints. The BEL/LOC constraints should be enrely specied either through
RTL or through XDC, but not a combinaon of both. Following is an example of BEL constraints
specied at the RTL.
Verilog le:
(*BEL="H6LUT",RLOC="X0Y0"*) LUT6 S0_LUTH (...);
(*BEL="G6LUT",RLOC="X0Y0"*) LUT6 S0_LUTG (...);
(*BEL="F6LUT",RLOC="X0Y0"*) LUT4 S0_LUTF (...);
(*BEL="E5LUT",RLOC="X0Y0"*) LUT4 S0_LUTE (...);
(*BEL="D6LUT",RLOC="X0Y0"*) LUT6 S0_LUTD (...);
(*BEL="C6LUT",RLOC="X0Y0"*) LUT6 S0_LUTC (...);
(*BEL="B6LUT",RLOC="X0Y0"*) LUT4 S0_LUTB (...);
(*BEL="A5LUT",RLOC="X0Y0"*) LUT4 S0_LUTA (...);
(*BEL="CARRY8",RLOC="X0Y0"*) CARRY8#(.CARRY_TYPE("DUAL_CY4"))
S0_CARRY8(...);
(*BEL="HFF2",RLOC="X0Y0"*) FD FD_out5 (...);
(*BEL="GFF2",RLOC="X0Y0"*) FD FD_out4 (...);
(*BEL="FFF2",RLOC="X0Y0"*) FD FD_out3 (...);
(*BEL="DFF2",RLOC="X0Y0"*) FD FD_out2 (...);
(*BEL="CFF2",RLOC="X0Y0"*) FD FD_out1 (...);
(*BEL="BFF2",RLOC="X0Y0"*) FD FD_out0 (...);
Note: The INIT string has been omied for simplicaon.
In the following example, the RPM is dened at the RTL but the BEL constraints are specied
through XDC.
Chapter 9: Defining Relatively Placed Macros
UG903 (v2022.1) June 1, 2022 www.xilinx.com
Using Constraints 162