© 2009 Microchip Technology Inc. DS39705B-page 17-15
Section 17. 10-Bit A/D Converter
10-Bit A/D
Converter
17
Functionally, MUX A and MUX B are very similar to each other. Both multiplexers allow any of
the analog input channels to be selected for individual sampling and allow selection of a negative
reference source for differential signals. In addition, MUX A can be configured for sequential
analog channel scanning. This is discussed in more detail in Section 17.4.4.1 “Configuring
MUX A and MUX B Inputs” and Section 17.4.4.3 “Scanning Through Several Inputs”..
17.4.4.1 CONFIGURING MUX A AND MUX B INPUTS
The user may select any one of up to 16 analog inputs to connect to the positive input of the S/H
amplifer. For MUX A, the CH0SA<3:0> bits (AD1CHS<3:0>) normally select the analog channel
for the positive input. For MUX B, the positive channel is selected by the CH0SB<3:0> bits
(AD1CHS<11:8>).
On certain PIC24F devices, users may also select the microcontroller’s internal band gap voltage
reference (V
BG) or one-half of the reference (VBG/2) as the positive input to the S/H amplifier. For
these devices, the CH0SA<4:0> bits (AD1CHS<4:0>) and CH0SB<4:0> bits (AD1CHS<12:8>)
select the positive input.
For the negative (inverting) input of the amplifier, the user has two options, selected by the
CH0NA and CH0NB bits (AD1CHS<7,15>, respectively). Setting either bit selects AN1 as the
multiplexer’s negative input; clearing the bit selects the current V
R- source designated by the
VCFG<2:0> bits (AD1CON2<15:13>).
17.4.4.2 ALTERNATING MUX A AND MUX B INPUT SELECTIONS
By default, the A/D Converter only samples and converts the inputs selected by MUX A. The
ALTS bit (AD1CON2<0>) enables the module to alternate between two sets of inputs selected
by MUX A and MUX B during successive samples.
If the ALTS bit is ‘0’, only the inputs specified by the CH0SA and CH0NA bits are selected for
sampling. When the ALTS bit is ‘1’, the module will alternate between the MUX A inputs on one
sample and the MUX B inputs on the subsequent sample.
If the ALTS bit is ‘1’ on the first sample/convert sequence, the inputs specified by the CH0SA bits
and CH0NA are selected for sampling. On the next sample/convert sequence, the inputs
specified by the CH0SB bits and CH0NB are selected for sampling. This pattern repeats for
subsequent sample conversion sequences.
17.4.4.3 SCANNING THROUGH SEVERAL INPUTS
When using MUX A to select analog inputs, the A/D module has the ability to scan multiple
analog channels. When the CSCNA bit (AD1CON2<10>) is set, the CH0SA bits are ignored and
the channels specified by the AD1CSSL register are sequentially sampled.
Each bit in the AD1CSSL register and AD1CSSH register (when implemented) corresponds to
one of the analog channels. If a bit in the AD1CSSL or AD1CSSH register is set, the correspond-
ing analog channel is included in the scan sequence. Inputs are always scanned from lower to
higher numbered inputs, starting at the first selected channel after each interrupt occurs.
The AD1CSSL or AD1CSSH bits only specify the positive input of the channel. The CH0NA bit
still selects the negative input of the channel during scanning.
Scanning is only available on the MUX A input selection. The MUX B input selection, as specified
by the CH0SB bits, will still select the alternating input. When alternated sampling between
MUX A and MUX B is selected (ALTS = 1), the input will alternate between a set of scanning
inputs specified by the AD1CSSL register and a fixed input specified by the CH0SB bits.
Note: Different PIC24F devices will have different numbers of analog inputs. Verify the
analog input availability against the particular device’s data sheet.
Note: If the number of scanned inputs selected is greater than the number of samples
taken per interrupt, the higher numbered inputs will not be sampled.